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4-30
Zero-Delay Buffer Mode
SV51005
2014.01.10
Figure 4-29: Example of Phase Relationship Between the PLL Clocks in Normal Compensation Mode
Phase Aligned
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
Dedicated PLL
Clock Outputs
The external clock output
can lead or lag the PLL
internal clock signals.
Zero-Delay Buffer Mode
In ZDB mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through
the device. This mode is supported only on the center and corner PLLs in Stratix V devices.
When using this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee
clock alignment at the input and output pins. You cannot use differential I/O standards on the PLL clock
input or output pins.
To ensure phase alignment between the clk pin and the external clock output ( CLKOUT ) pin in ZDB mode,
instantiate a bidirectional I/O pin in the design. The bidirectional I/O pin serves as the feedback path
connecting the fbout and fbin ports of the PLL. The bidirectional I/O pin must always be assigned a single-
ended I/O standard. The PLL uses this bidirectional I/O pin to mimic and compensate for the output delay
from the clock output port of the PLL to the external clock output pin.
Note: To avoid signal reflection when using ZDB mode, do not place board traces on the bidirectional I/O
pin.
Altera Corporation
Clock Networks and PLLs in Stratix V Devices
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